The present invention relates to data processing systems and more particularly to control store addressing architecture and methods associated therewith.
Most data processing systems now include control stores which include so-called firmware in order to control the operation of such systems. Included in such firmware are several main line routines and, in addition, subroutines which are shared by the main line routines. When switching from a main line routine to a subroutine or when suspending the operation of a routine for any reason, the address of the next location or instruction in such routine must be saved in order to insure return to the proper instruction of the routine which has been suspended. One of the techniques used in the prior art includes the implementation of an address incrementer and a return address register. Using this implementation, when a subroutine entry is performed, the incremented address is saved in the return address register as the address for the control store upon return from the subroutine. As can be seen, this prior art apparatus requires incrementer logic, as well as associated control logic, which, although adequate, does consume physical space and increases the cost in the manufacture of the particular system.
It is accordingly a primary object of the present invention to provide a data processing system having an improved control store addressing technique.